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CMOS-Compatible Process

A Deeper Look at eDRAM Cell Structure

The compatibility advantage of NEC Electronics' embedded DRAM (eDRAM) can be seen by comparing it with conventional DRAM cells. The conventional DRAM-Type cell (Figure 3) lacks the silicide technology used in logic transistors. It is virtually identical with the commodity DRAM cell (Figure 1), but this comes at the expense of compatibility with the CMOS logic. Moreover, performance typically lags one or two generations behind the logic process.

The conventional ML-type embedded cell (Figure 2) is designed for use in eDRAM, but it also inherits the commodity DRAM cell structure, resulting in a significant process mismatch with high-performance logic. Gate electrodes and all other transistor features must be fabricated separately from the standard process CMOS logic. This requires many additional process steps, driving up the cost.

The conventional ML-type embedded cell (Figure 2) is designed for use in eDRAM, but it also inherits the commodity DRAM cell structure, resulting in a significant process mismatch with high-performance logic. Gate electrodes and all other transistor features must be fabricated separately from the standard process CMOS logic. This requires many additional process steps, driving up the cost.
By contrast, the NEC Electronics' embedded DRAM cell (Figure 4) has a structure based on the standard CMOS logic process, not a commodity DRAM process. Our eDRAM and standard CMOS are thus fully compatible.

Full-Metal eDRAM Boosts Speed

Several key NEC Electronics technologies provide performance and reliability advantages over other suppliers of embedded DRAM. One of NEC Electronics' greatest advantages is its full-metal embedded DRAM. This unique process uses various types of metal for major components of the embedded DRAM device element, which eliminate a large amount of parasitic and capacitor resistance and capacitance, thus dramatically improving DRAM speed while reducing power consumption.

Higher speeds through lower RC delay

This reduction in the eDRAM cell's R parasitics dramatically improves eDRAM speed while reducing power consumption. Most noticeably, the cell's node resistance (Rnode) is more than a thousand times lower than that of other eDRAM cells. Because NEC Electronics' eDRAM uses silicide even in the eDRAM cell area, our cell transistor's on-resistance (Ron) is 1/3 to 1/4 lower and the on-current (Ion) is 2 to 4 times higher than that of other suppliers' eDRAM. At the same time, the lower resistance reduces the IR drop across the cell, enabling the use of lower operating voltages for reduced power consumption.

Further, our use of W/TiN as the bit line material achieves thinner bit lines, which minimize the parasitic capacitance between bit lines. This strategy reduces the corresponding RC delay, which permits much higher speeds than otherwise would be possible.

Overall, the NEC Electronics process offers both fast logic and fast eDRAM, while minimizing extra process steps.

Yet another key technology advantage for NEC Electronics lies in the way the eDRAM capacitor structure works with chemical mechanical polishing (CMP). While conventional box-type stacked capacitor cells leave a fair amount of height difference between the DRAM cell and CMOS logic area in a chip, the NEC Electronics cylinder-type stacked capacitor structure dramatically reduces the height difference, resulting in a uniform surface over the entire chip after CMP for better yield and lower cost.

130 nm Node Technology

Rnode Ron NEC UX5D 15K 10K Commodity DRAM 20K~40K 30K~40K Conventional ML 30K~70K 30K~40K

Low-Temperature Capacitor Process

Another major NEC Electronics technology advantage is the ability to fabricate the capacitors at the heart of eDRAM cells at about half the temperature of commodity DRAM and well below the temperature used in a normal CMOS logic process. This low-temperature process is important because NEC Electronics fabricates CMOS logic before the embedded DRAM capacitors, so temperatures must be kept low to avoid degrading the performance of the CMOS logic.

The success of NEC Electronics' low-temperature capacitor process can be seen by comparing the CMOS transistor characteristics before and after eDRAM capacitor formation. These measurements show that the transistor performance is identical in both cases. Using the NEC Electronics process, your CMOS logic will run at the same high speed either with or without eDRAM.

Reducing Global Height Difference Improves Yield

Yet another key technology advantage for NEC Electronics lies in the way the embedded DRAM capacitor structure works with chemical mechanical polishing (CMP). While conventional box-type stacked capacitor cells leave a fair amount of height difference between the DRAM cell and CMOS logic area in a chip, the NEC Electronics cylinder-type stacked capacitor structure dramatically reduces the height difference, resulting in a uniform surface over the entire chip after CMP for better yield and lower cost.

Box-type Capacitor (Competitors)

Cylinder-type Capacitor (NEC Electronics)

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