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Easy Integration
For speed and simplicity, NEC Electronics configures eDRAM read and write procedures to work like those of SRAM. On consecutive reads, writes and alternating read/write cycles, NEC Electronics eDRAM provides SRAM-like sequences that have no idle cycles. By eliminating the need for the complex commands associated with SDRAM, our eDRAM is easy to integrate into your SoC design.
SRAM-Like Access (read)
SRAM-Like Access (write)
SRAM-Like Access (read and write)
Row-only Refresh (ROR)
tCK = 5 ns for 130nm CB130; 4ns for 90nm
Embedded DRAM must be refreshed periodically and refresh is the only restriction of eDRAM. The refresh scheme of NEC Electronics eDRAM is
row-only-refresh (ROR). One row must be either refreshed or accessed by read or write operation within the maximum data retention time (tREF). One clock cycle is required to refresh one row.
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