Please note that JavaScript and style sheet are used in this website,
Due to unadaptability of the style sheet with the browser used in your computer, pages may not look as original.
Even in such a case, however, the contents can be used safely.

Technology > Advanced Process Technology > Embedded DRAM >

NEC Electronics eDRAM Process Advantages

NEC Electronics has pioneered the use of unique materials that are fully compatible with standard CMOS processes. NEC Electronics introduced Ta₂O₅into the dielectrics of DRAM capacitors in our first CMOS-compatible eDRAM, at a time when commodity DRAM devices had not yet utilized Ta₂O₅. We introduced the MIM capacitor in 0.15 µm and 0.13 µm eDRAM with the Ta₂O₅dielectric. Toward 90 nm eDRAM and beyond, NEC Electronics started the development of ZrO₂dielectric capacitors, now introduced as MIM2. These materials have been shown to boost eDRAM performance on every process node. They promise a clear technology roadmap for eDRAM on 55 nm and beyond.

Key Technologies for eDRAM Cells

	UD1H 350 nm	UD2 250 nm	NED3 180 nm	UX4D 150 nm	UX5D 130 nm	UX6D 90 nm	UX7LSeD 55 nm
Cell structure	COB	COB	CUB	CUB	COB	COB	COB
Cell size (µm²)	1.24	0.67	0.51	0.43	0.35	0.22	0.12
Bit line materials	WSi	WSi	W/TiN	W/TiN	W/TiN	W/TiN	W/TiN
Word line materials	WSi/Poly	CoSi	CoSi	CoSi	CoSi	CoSi	NiSi
Cell Tr. salicide	None	CoSi	CoSi	CoSi	CoSi	CoSi	NiSi
Capacitor type	PIP	PIP	MIS	MIM	MIM	MIM-2	MIM-2
Dielectric materials	Si₃N₄	Si₃N₄	Ta₂O₅	Ta₂O₅	Ta₂O₅	ZrO₂	ZrO₂
Max temperature	900°C	850°C	800°C	450°C	450°C	400°C	400°C
Ref. dielectric of CMOS	SiO₂	SiO₂	SiON	SiON	SiON	SiON	HfSiOx

Abbreviations of capacitor types are as follows:
PIP: Poly/Insulator/Poly
MIS: Metal/Insulator/Poly-silicon
MIM: Metal/Insulator/Metal
Commodity DRAM capacitors require >1,000 °C thermal treatment.

Evolution of NEC Electronics eDRAM

Unlike most other embedded DRAM, NEC Electronics' eDRAM structure is based on the standard CMOS logic process – not a commodity DRAM process. NEC Electronics' eDRAM and standard CMOS process are thus fully compatible. Adding eDRAM to your ASIC requires only eight or nine additional masks, and all steps are handled in a single fabrication line. In contrast, competitors require 13 to 20 extra steps and two different fabs – one for CMOS and another for the DRAM.

The above drawings of eDRAM cells show the advantages that the NEC Electronics eDRAM structure has over that of competitors. For a size reference, note that the salicided transistor between the bit line and the capacitor in the NEC Electronics cell is a standard CMOS device. The deep-trench capacitor structure used by competitors dwarfs this transistor, as does the height of their metal 1. The minimal height differential in the NEC Electronics' eDRAM structure makes it possible to keep a uniform surface over the entire chip after chemical/mechanical polishing (CMP) for better yield and lower cost.

The NEC Electronics metal/insulator/metal (MIM) capacitor structure has followed a steady process shrink and also benefits from new materials that enhance performance. Most notably, the unique ZrO2 dielectric introduced in our 90 nm eDRAM offers a number of benefits while maintaining full CMOS compatibility.

In addition to this process compatibility, our eDRAM provides functional compatibility by operating at a single voltage identical to the core voltage of standard CMOS. This SoC-friendly eDRAM gives you SRAM-like access as well as features such as eBIST for configuring self-test, eFuse for swapping-out failed cells in the field, and self-refresh mode.

Low-temperature capacitor process

Another major NEC Electronics technology advantage is the ability to fabricate the capacitors at the heart of eDRAM cells at about half the temperature of commodity DRAM and well below the temperature used in a normal CMOS logic process. This low-temperature process is important because NEC Electronics fabricates CMOS logic before the eDRAM capacitors, so temperatures must be kept low to avoid degrading the performance of the CMOS logic.

Using the NEC Electronics process, your CMOS logic will run at the same high speed either with or without eDRAM.

Materials Advantages

The zircon dioxide (ZrO₂) dielectric used in our 90 nm eDRAM represents a significant step forward in enhancing performance for a fully CMOS-qualified process. ZrO₂'s high dielectric constant, low leakage and low-temperature-formation characteristics make it ideal for eDRAM.

Comparing ZrO₂ against tantalum- and hafnium-based dielectrics (Ta₂O₅ and HfO₂, respectively) shows the zircon advantage. These alternative dielectrics are used in other DRAM applications, and Ta₂O₅ is used in previous generations of NEC Electronics eDRAM. The following tables show that in capacitance as well as cell area and height, ZrO₂ exhibits much better characteristics for eDRAM use.