UX6 Process Technologies

NEC Electronics' UX6 standard CMOS process brings you leading-edge 90nm technologyhigh-reliability copper interconnect plus multiple gate-oxide choices for performance options that are ideal for high-density, high-speed system solutions as well as low-power applications. The range of applications includes mobile devices, communication systems, network servers, wearable computers and a wide variety of consumer products.

NEC Electronics' UX6 process technology provides 1.0V transistor operation and super-fine 60nm gates to meet the broad spectrum of requirements from ultra-high performance to low power consumption. State-of-the-art ArF lithography and high-precision etching enable a single chip to integrate 100 million logic gatesapproximately twice as many gates as previous-generation chips. By taking advantage of UX6 high-performance transistors and as many as nine layers of copper/low-k hierarchical interconnects, you can achieve GHz-range operation. The UX6 process' proven superior copper interconnect reliability includes effective countermeasures against copper stress-induced voiding.

VERSATILE TRANSISTOR CHOICES

Inheriting the multi-feature concept of NEC Electronics' previous UX generations, the UX6 process offers a wide range of transistor performance levels, from high speed to low leakage. The UX6 process also gives you three I/O voltages. Our multi-oxide technology allows you to mixn different gate-oxide choices.

The following transistor choices allow you to balance speed with power.

For high performance at low voltage, the UX6 process incorporates techniques that reduce gate-dielectric thickness and thus enhance performance:

ROBUST INTERCONNECT RELIABILITY

Proven across vast numbers of fabricated test samples, NEC Electronics' UX series delivers superior reliability based on carefully refined copper interconnect technology. This reliability is in contrast to the issues encountered in some processes with copper stress-induced voiding. NEC Electronics already solved this issue in the 130nm-generation UX5 process and has implemented similar countermeasures in the UX6 process. The solution combines single- and dual-damascene structures (trenches for copper interconnect) along with post-copper-formation treatment. With these techniques, NEC Electronics has proven high reliability at process qualification.

SRAM CHOICES

The UX6 process offers several SRAM cell sizes to meet various performance requirements:

HIGHLY ACCURATE INTERCONNECT MODELINGDISSOLVING THE GAP BETWEEN DESIGN AND ACTUAL SILICON

As design complexity has soared with each process generation, interconnect characteristics variance and signal integrity have emerged as critical issues. Beginning with the UX6 generation, NEC has addressed these issues by adopting a new interconnect modeling methodology. NEC now characterizes the actual interconnect shape variance depending on line/space dimensions and surrounding density from actual silicon data and ports the variance information into Layout Parameter Extraction (LPE) models. These models help ensure that your simulations mirror the actual physical characteristics of your chip. Read our press release for more information on NEC Electronics' highly accurate copper-interconnect modeling methodology.
NEC Electronics is a technology leader in such process-linked design techniquesa key enabler for advanced designs.

• Press release about "Highly Accurate Copper-Interconnect Modeling Methodology"

IP DESIGN RULE COMPATIBILITY FOR IP REUSE

To give you immediate access to IP cores proven with the standard technology, the UX6 design rules and generic device performances are fully compatible with standards developed in Japan. Supporting these standards also helps accelerate the circulation and standardization of IP cores, ensuring the availability of a broad range of essential IP choices.