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Product Lineup
NEC Electronics offers a wide variety of Gate Arrays, ranging from 0.5µm to the latest 0.15µm.
Whatever your field or usage, you'll be sure to find a product to meet your needs.
Gate Arrays and Embedded Arrays Pamphlet
| Choosing the Right Product | Product Lineup | Product List |
| Package | Macro | Selector Tool |
Choosing the Right Product
- To select a product based on the supply voltage, refer to Product Lineup or Products List.
- To select the package and master best suited for the development set, use the Master/Package Retrieval.
Product Lineup
Product List
| Series | ||||
|---|---|---|---|---|
| Process | Wiring layers | Power supply voltage | Maximum operating frequency |
Gate Size |
CMOS-N5  |
||||
| 0.5µm | 2Layers | 4.5-5.5V 2.7-3.6V (2.7-5.5V) |
5V:60MHz 3.3V:33MHz |
1.5K-93K |
| CMOS-9HD |
||||
| 0.35µm | 3/4Layers | 2.7-3.6V (5V tolerant) |
100MHz | 11K-1.51M |
| EA-9HD |
||||
| 0.35µm | 3/4Layers | 2.7-3.6V 3.3V/5.5V (5V Full swing output enabled) |
100MHz | 10K-1.39M |
| CMOS-12M |
||||
| 0.15µm | 5/6Layers | 1.5V(internal) 1.5V/1.8V/2.5V/3.3V (4 Power supplies max) |
Embedded type: 200 MHz (local:300MHz) SOG type: 250 MHz |
62K-2M (RAM:96K-2.7Mbits) |
Package
NEC Electronics offers a wide variety of packaging options for Gate Arrays, with special emphasis on small-outline packages with low pin counts. All of our packaging solutions are available in RoHS-compliant versions.
Master / Package Retrieval
Although customers can select their optimum package from among the many package types listed in this table, some selections may involve implementation issues.
Macro
A wealth of macros are provided with NEC Electronics Gate Arrays and Embedded Arrays.
For example, there are I/O macros that can be used to implement a high-speed interface (SSTL2, SSTL3, LVDS, etc.) and megamacros for realizing serial controller or parallel interface functions.
In addition, Embedded Arrays enable mounting of cell-based IC memory, which can help to realize higher integration.
Selector Tool
- The following tools use Java technology.
Die Estimator
The Die Estimator (EstWeb) allows you to select the best-suited master based on the required macros and number of gates.
Note that the optimization master estimation tool is currently being improved (by updating the data of packages that can be used with CMOS-10HD Series masters).
For details about the CMOS-10HD Series and packages, contact us.
Die Estimator
Inquiry Concerning Gate Arrays
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