Please note that JavaScript and style sheet are used in this website,
Due to unadaptability of the style sheet with the browser used in your computer, pages may not look as original.
Even in such a case, however, the contents can be used safely.

Products > ASIC > Gate Arrays and Embedded Arrays > Development Environment >

Design Environment

A design environment (design tool) is necessary in designing Gate Arrays and Embedded Arrays.
For the Gate Arrays and Embedded Arrays design environment, NEC Electronics allows for a tool set selection and combination of NEC Electronics' in-house developed OPENCAD design tool and other third party tools, providing flexibility to meet customers' design environments.

OPENCAD®

Function	Tool
Function	NEC Electronics	3rd party
Framework	OPENCAD V5, OPENCAD CMOS-12M^*1	-
Schematic editor	Vdraw	-
Logic synthesis	-	Design Compiler
Test pattern creation	Wave Editor	-
Logic verification	V.sim	ModelSim, NC-Verilog, VCS
Timing verification	Tiara	PrimeTime
Formal verification	-	Conformal-LEC, Formality
Design for testing	NEC_SCAN/NEC_BSCAN/ Robust Scan, opc_testact	DFT Compiler, TetraMax
Placement and routing	Galet	SoC ENCOUNTER^*1

Note(*)

Only for CMOS-12M

OPENCAD Platform

OPENCAD	OS
Solaris	Solaris 10 (64 bit)
Linux^*1	RedHat EnterPrise 4.0 AS/WS/ES X86^*2

Note(*)

OS required for CMOS-12M
Operation not guaranteed for Red Hat Linux 7.x/8/9.
Operation guaranteed for x86 CPUs only.
Depending on the OS, some tools may not be supported.

Trademark

Gate Arrays and Embedded Arrays Home