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CMOS35
UC-1H (CB-9VX)

CMOS25
UC-2 (CB-10VX)

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(12/2006) (278 KB)

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UC-2 0.25 µm CMOS (5Al)

Process Features

Twin Well CMOS
LOCOS Isolation
Gate Oxide 60 A
Gate: 0.25 µm (width) 0.60 µm (pitch)
Contact Diameter: 0.36 µm
3 to 5 Al capability
1-4 Al: 0.44 µm (width) 0.84 µm (pitch)
5 Al: 3.0 µm (width) 6.0 µm (pitch)

Device Features

Supply Voltage: 2.5 0.2 V (normal transistor)
Supply Voltage: 3.3 0.3 V (milti-oxide transistor)
Min. Transistor Width: 0.56 um
Min. Transistor Pitch: 1.00 um (Min. Gate Pitch w/ Contact)

CMOS Electrical Parameters

NMOS Device:	Target	Min	Max	Units
BVDSN (50/0.25 @1µA Vgs = 0)		5		V
Vtn (50/0.25 @1µA Vds=2.5V)	0.45	0.35	0.55	V
Ionn (50/0.25 @Vds=Vgs=2.5V)	21.25	20.25	22.75	mA
PMOS Device:	Target	Min	Max	Units
BVDSP (50/0.25 @-1µA Vgs = 0)			-5	V
Vtp (50/0.25 @-1.0 µA Vds=-2.5V)	-0.45	-0.55	-0.35	V
Ionp (Vds=Vgs=-2.5V)	-9.75	-10.75	-9.25	mA

Questions? Contact our foundry team.