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EMMA2SL/P   (µPD61215)

Low-cost LSI products with enhanced security functions for set-top boxes



Overview

The EMMA2SL/P (µPD61215) decoder provides powerful, highly integrated, single chip solutions for digital STB and iDTV, and has a number of feature variants to provide the most cost-effective solution for Pay-TV applications.
This product features a built-in security function to prevent unauthorized reception of paid digital broadcasting and incorporates an external VCXO circuit in addition to a high-end processor and a high-speed memory interface. Without a doubt, EMMA2SL/P delivers industry-leading performance at a industry-pleasing price.


Target System

  • Low-end STBs and iDTVs with advanced security features

Product specification

Product specifications
Internal CPU
  • Main CPU: Application/RTOS/API/BIOS processing purposes
    • MIPS32® 4KEc® core
    • 284 MIPS @ 186 MHz
    • Supports MIPS II™ and MIPS-16 instruction sets
    • Cache size: I-Cache: 4 KB, D-Cache: 4 KB
  • Sub CPU: Decode processing purposes
    • MIPS32® 4KEm® core
    • 284 MIPS @ 186 MHz
    • Supports MIPS II™ and MIPS-16 instruction sets
    • Cache size: I-Cache: 4 KB, D-Cache: 4 KB, Scratch Pad: 8 KB
Memory interface
  • RAM Memory I/F
    • Unified RAM Memory I/F: CPU/MPEG decoding/display/graphics, etc.
    • DDR Memory I/F: Supports 16 to 128 MB capacity
  • ROM Memory I/F
    • Supports NOR/NAND Flash ROM
    • Supported maximum capacity: 64 MB
MPEG stream processor
  • NEC Electronics original processor core
  • Software processing architecture
  • Stream I/F: Parallel/serial input x 1
  • MPEG2 TS (Transport Stream)
  • Maximum TS processing rate: 100 Mbps
  • 36 PID filters (including Video x 1, Audio x 2, PCR x 1)
  • 32 section filters (8-byte/16-byte depth)
  • Supports HSD (High Speed Data) port output
MPEG video decoder
  • Supports MPEG2 MP@ML 1 system decoding
Audio controller
  • Supports MPEG1/MPEG2 layer 1/2
  • Supports DAO (Digital Audio Output) L/R output
  • Supports SPDIF output
Graphics engine
  • 2D BitBLT
Display
  • 5 planes: BG (Back Ground), Still, Live Video, and OSD x 2 planes
  • 256 gray-scale a-blending function
  • Real-time video scaling (1/4 to 8/1H/V)
  • OSD anti-flicker filter
Video encoder
  • NTSC/PAL video encoder
  • Supports Closed Caption, WSS, Video ID, VPS, and Teletext
  • 4-channel DAC for simultaneous RGB/YC&CVBS analog output
  • ITU-R BT.656 digital output function
Peripherals
  • FUART x 2
  • Smart Card I/F x 2
  • I2C x 2
  • Clocked Serial I/F
  • Timer: System, WDT, RTC
  • IR receiver
  • General PIO
Process
  • 0.15 µm CMOS process
  • Power supply: 3.3 V, 2.5 V, 1.5 V



Block Diagram

Block Diagram


Product Lineup

T.B.D




This device is protected by U.S. patent numbers 5,583,936; 6,516,132; 6,836,549; and 7,050,698, and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited.
This Device can only be sold or distributed to Authorized Buyers.



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