CB-90 Packaging Options
NEC Electronics offers a variety of ball grid array packaging configurations for CB-90 customers to support a broad number of applications. Click here for a list of supported packages.
IP Lineup
Within the CB-90 family, NEC Electronics offers a wide range of IP cores and high-performance I/Os. In addition to SRAM memory macros, NEC Electronics offers embedded DRAM macros from 4Mb to 16Mb in various configurations. Click here for more information on featured IP cores.
High Integration, High Speed and Low Power Consumption
NEC Electronics' CB-90 family is built on the advanced UX6 microfabrication process to achieve high integration and support for up to 100 million usable gates. High clock speeds are possible because of 1-volt, high-speed CMOS transistors that realize ultra-low power using a gate length of 60 nm, all-copper wiring and low-k (k = 2.9) inter-metal dielectrics.
The use of up to nine levels of all-copper wiring (minimum wiring pitch of 0.28 µm) in the CB-90 libraries enables both increased density and higher reliability. Moreover, the use of low-resistance copper material enables NEC Electronics to realize thinner wiring layers, contributing to higher speed and lower power consumption due to reduced wire capacitance.
Low gate-leakage is achieved by combining a radical nitridation process, which lowers the leakage current of the gate oxidized film, and a triple-oxide process that forms MOS transistors with three different gate-oxidized film thickness. Mixing optimum transistors according to the target circuit performance lowers power consumption by approximately 40% compared to power consumption of previous generations. The use of low-power techniques including a multi-power-supply design flow and automatic voltage control technology further reduces power consumption.
Using cells with low standby-leakage prevents the usual increase in leakage that accompanies a smaller geometry process and reduces leakage to the few µA required for backup operations at the chip level. Also, in normal operation at 1.0 volts, using high-density cells in circuits that perform high-speed signal processing increases speed and reduces power consumption. The combination of low standby-leakage high-density cell libraries and unique low-power design techniques enables NEC Electronics to realize sophisticated power management in its system LSI devices. |