Cell-Based ASICs

CB-130

Description

With NEC Electronics America's CB-130 technology, your design goals for the lowest power and highest performance can be achieved by mixing different transistors to suit requirements. With CB-130, system-on-chip (SoC) is not merely a turn of phrase. High-density memory, CPU cores, and high-speed interfaces can be bundled in one chip.

Features

• 0.095 µm (drawn) silicon gate CMOS process
• Four transistor characteristics (low power, mid-range power, high speed, ultra-high speed) selectable on the same chip
• All-layer copper wiring with up to nine metal layers
• Up to 52 million gates available
• High-speed system frequency up to 800 MHz (system-dependent)
• 1.2V core voltage optimized architecture
• Extreme low power dissipation down to 5 nW/MHz/gate
• 1.2V, 1.8V, 2.5V, and 3.3V I/O voltage options
• Flexible I/O structure supports LVDS, HSTL, SSTL, GTL+, PECL, AGP, PCI
• High pin count packages with over 2000 pins
• Various package types: QFP, FPBGA, TBGA, ABGA, PBGA, FCBGA

Chip Design Concept

Restrictions apply to the combination of I/Os, libraries or macros.
 

Product Outline
Metal layer		Up to 9 (highest layer is used for FCBGA interconnect)
Available gate count (max.)		52 million
Number of pads		> 2000
System frequency		800 MHz
Gate delay (FO = 2, 2NAND, I = 0)	Standard	19.0 ps
	High-Speed	16.2 ps
Gate power consumption	Low-Power	7 nW/MHz/gate
	Standard	9 nW/MHz/gate
Power supply voltage		1.2 V ±0.1 V
Ambient operating temperature		-40 to +85°C
Interface level		1.2 V, 1.8 V, 2.5 V, and 3.3V
Technology		Standard cell 0.095 µm silicon gate CMOS, all-layer copper wiring

CB-130 Families

Family	Library	Transistor Characteristic
CB-130H	UH12	Ultra-high speed
	H12	High speed
CB-130M	H9	High speed
	M9	Mid-range power
CB-130L	L9	Low power

In CB-130 technology, the ASICs are designed using one family. Hard macros, which are implemented with another family, are inserted then.  

Architecture

Four transistors optimize power dissipation in the CB-130 family, without a drop in performance. Together with the low-k intermetal dielectrics (k = 2.9), this allows clock speeds to reach 800 MHz. Area I/Os for FCBGA (flip-chip BGA) are enabled using the topmost metal layer, for the latest in package technology. Fabrication of the cell-based ICs is based on one of the world's most advanced semiconductor processes.

Intellectual Property

CPU cores such as the V850™ and VR41xx™ cores plus peripherals, are currently under development. Application-specific cores for networking (Ethernet, ATM), graphics (DRAC, 2D/3D accelerator), consumer (MPEGx, JPEG), mobile (DSP) and PC (USB, PCI) and many more help to build a genuine SoC design. Analog cores such as those for PLL and A/D or D/A conversion round out this wide range of macros.

High-Speed Serial Interfaces

High-speed interface macros for networking, telecommunication and EDP applications, covering the range from 150 Mbps to 3.2 Gbps, support the design of high-performance systems.