Cell-Based ASICs

CB-12

Description

NEC is worldwide the first to offer Cell-based IC in 13µm drawn process technology called CB-12. Featuring the selection of three different transistor characteristics on the same chip for achieving the optimum combination of high performance, effective use of area, extreme low power consumption, CB-12 is targeted to enable the implementation of System-on-Chip (SOC) for wide range of application such as telecomm, network, consumer, automotive, industrial. To meet the challenge of both complex system-level design and fast time-to-market, NEC is supplying total design support for hardware, software design and system integration.

Features

• 130nm (drawn, 110 nm effective) Cobalt Salicide CMOS process
• Three transistor characteristics (low power, Standard, High performance) selectable on the same chip
• Metal layer options: 5/7/8 Metal layers
• Available gate count from 1 million to 32 million gates
• High speed: gate delay of 15.1 ps (standard, 2-NAND, Fanout = 2, L = 0)
• Core voltage 1.5 V
• Extreme low power dissipation down to 7 nW/MHz/gate
• Optimized 1.5 V architecture
• I/O voltage: 2.5 V, 3.3 V, 5 V tolerant
• Flexible I/O structure supports LVTTL, GTL+,HSTL, SSTL, PCI, USB, AGP, LVDS, pECL
• High pin count packages up to 2600 pins
• Various package types available: QFP, FPBGA, TBGA, ABGA, PBGA, FCBGA Features ROM ROM Logic

Product Outline
Master Name		µPD80xxx (44 die steps)
Metal layer		5 / 7 / 8
Available gate count (max.)		26 million / 32 million / 32 million
Number of pads		(max.) 1500-2700
Toggle frequency (standard)		5.4 GHz
Gate delay (FO = 2, 2NAND, I = 0)	Standard	15.1 ps
	High-Speed	21.2 ps
Gate power consumption	Low-Power	7 nW/MHz/gate
	Standard	13 nW/MHz/gate
Power supply voltage		1.5 V ± 0.15 V
Ambient operating temperature		-40 to +85°C
Interface level		2.5 V/3.3 V CMOS, LVTTL
Technology		0.18um metal pitch, 130nm transistor

Architecture

Manufactured with NEC's advanced Cobalt-salicide process, the CB-12 SOC technology offers the choice of three transistor characteristics for enabling an optimum configuration of performance/low power/high-integration targeted area partitioning on the same chip. The selectable Ion/Ioff switching characteristics, which can be used e.g. to achieve an optimum speed for CPUs and low power consumption for user logic, enables the imple-mentation of a high performance application requiring the minimum of electrical power.

Interfacing

The CB-12 I/O structure enables the broad variety of interfacing support. I/O voltage of 2.5 V, 3.3 V will be supported as well as 5 V tolerant buffers and PCI buffers. GTL+, HSTL, SSTL, AGP, USB, LVDS, pECL standard will be supported for high-speed interfacing. Pad pitches of 50 µm and 80 µm support a broad range of package selection like QFP, FPBGA, TBGA, ABGA, PBGA, FCBGA with up to 2600 Pins to meet all kind of appliances.

Leading edge system integration implies a total solution with both software / hardware design and integration.

System-on-Chip Integration

The rich portfolio of NEC's ASIC pre-verified MegaMacros increases the hardware design efficiency of a typical System-on-Chip project, which requires processor/DSP cores, memories, peripherals and analog functions. The CPU architecture selection ranges from MIPS architecture to NEC's V850 and ARM7, all kind of high-speed and low-speed bus peripherals like memory controllers, system controllers and communication function will be provided. To enable the easy software integration NEC's CPU cores are supported by a number of industry-standard software development tools including OS, debuggers and emulators as well as a broad portfolio of firmware for various appliances. For the smooth concurrent design and integration, NEC offers the support for industry leading Hardware/ Software co-verification tools.

Test

For testing complex System-on-chip, a new approach of block level testing is required which must ensure sufficient testing with high fault coverage in a reasonable engineering time. In addition to conventional Scan test methodology NEC will support NEC's TestBus concept and Built-in-Self-Test (BIST) for memory macros.

System-on-Chip Design Support

For meeting the challenge of a very deep submicron design and system-level integration, NEC takes two leading edge design approaches:

• System-level design including Hardware/ Software Co-simulation/Co-Verification on a block-based system design approach
• NEC's sophisticated design framework OpenCAD V6 including physical floor planning, timing driven layout, hierarchical design.