Cell-Based ASICs
CB-10VX
Technology
node |
Max.
available
gates |
Max. I/Os |
Delay time
(F/O=2, 2-input NAND) |
| 0.25 µm |
19,519K |
2016 |
77 ps |
|
|
 |
| |
Documentation
Please use our Tech Support Form if you wish to request copies of the ASIC documentation: |
|
|
| |
| |
- Block Library - CMOS 2.5V
(12/1999) (2451 KB)
|
|
|
| |
- Block Library - TTL 2.5V
(04/2000) (2499 KB)
|
|
|
| |
- Design Manual
(01/2001) (1492 KB)
|
|
|
| |
- Design Manual - Analog Macro (High-Speed D/A Converter)
(06/2000) (471 KB)
|
|
|
| |
- Design Manual - Memory Macro
(06/2000) (387 KB)
|
|
|
|
SITE MAP
LEGAL
